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Code: EP154
ISBN: 0 901150 43 6
Release Date: January 2003

Description

This book, written for both engineers and students of electronics technology, examines the subject of chip scale packaging. Chip scale packaging was one of the last major developments in the arena of electronics packaging and assembly in the 20 th century and one of the most exciting. The technology has enabled the miniaturisation of electronics packaging to progress to the threshold of its practical limits. No previous packaging technology has ever taken hold so fast or spread so rapidly as chip scale packaging technology.

There are manifold reasons for this phenomenon and, in this book, authors from Asia, Europe and the United States have prepared chapters to help bring to the reader an understanding and appreciation not only of specific chip scale packaging concepts but also of the scope and depth of this important new technology.

Chip scale packaging represents what may well be the last stop in electronics packaging. While it is true that some advocates of bare die technologies suggest that the package is a useless, even performance robbing addition to an electronics assembly, the arguments offered by the authors of this book provide a solid case for IC packaging technology. IC packaging technologies, they argue, are especially important in view of the many different materials and processes that are used in the manufacture of an electronics assembly. In contrast to their detractors, packaging engineers do not eschew bare die solutions; rather they embrace them in order to create new more useful packages. They largely recognise that bare die solutions are simply packaging in situ options. What is lacking, however, are the many benefits of a package, such as protection, standards and ease of use by the existing assembly infrastructure. Thus CSPs are poised to deliver on the promises left unfulfilled by multichip modules. They offer the combined benefits of bare chips with the numerous benefits of packages.

This book has been organised into three sections. Section 1 reviews the development of the CSP market and looks at applications. It also looks at the industry infrastructure that must support the chip scale packaging revolution. Clearly, no technology can advance very far without such structural support. For CSPs critical support areas include the materials of manufacture and assembly. With the convergence of the various elements of electronics assembly, it is becoming increasingly important that those elements work more closely. Standards are vital to making such a transition and thus one chapter is devoted to this important topic.

Section 2 of the book looks at some of the various chip scale packages being used and includes a discussion of flip-chip technology, which is a key assembly technology used in the construction of CSPs. While, according to published literature more than 100 different package types have been proposed, most are variations on a few common themes and only a few of those basic themes have seen volume deployment. We have attempted to provide the reader with chapters covering the most relevant offerings on the market or in development, rather than deluge and confuse the reader with the full complement of subtly different options of the fundamental themes.

The last two chapters of this section examine subjects of growing interest to the electronics packaging community, 3D or stacked chip packaging and wafer-level packaging, wherein the integrated circuit and package are poised to be fused into what might well be called an integrated package. These subjects are highly charged concepts that are likely to be of continuing future interest to the electronics industry.

The last section of the book examines chip scale package reliability. The reliability of these miniature packages is of great concern to would-be users. There is a general recognition of the effects of joining materials of greatly differing coefficients of thermal expansion and nowhere is this issue more relevant than in the joining of low CTE silicon dominated packages to high CTE organic substrates. Perspectives are provided from both Europe and the United States, which will hopefully serve to advance the reader’s understanding of this extremely important topic.

This book was a long time in development and much has changed and evolved during the time of writing. Making the decision as to when to go to press is a difficult one. We believe we have captured and made coherent most of the important issues related to chip scale packaging in this text. Clearly there will be continuing work in this area and related fields. The authors and editors hope that this book will prove of enduring value to both electronics packaging practitioners and serious students of electronics packaging technology.

About the Authors

Joseph Fjelstad is an associate of Pacific Consultants LLC, a product engineering and analysis company located in Mountain View, CA. Mr Fjelstad has more than 28 years of international experience in electronics interconnection and packaging technology. Prior to joining Pacific Consultants, he was with Tessera, a leader in chip scale packaging, where he was awarded the first corporate fellowship for having helped to refine and introduce the internationally known µBGA™ chip scale package and for his numerous inventions.

Mr Fjelstad has served in a wide variety of capacities over his career including analytical chemist, manufacturing chemist, process engineer, quality manager and research & development manager. He also served as educational director in the IPC in the early 1980s. A receipient of the IPC President’s Award, Mr Fjelstad has remained actively involved in the IPC as chairman of various committees and currently member of the National Electronic Roadmap committee for Electronic Interconnections. Mr Fjelstad has authored numerous technical papers and technical journal articles and is frequently sourced for comment by technical editors and reporters. He has authored or co-authored several books on various electronics packaging related subjects. Book titles include: ‘An Engineer’s Guide to Flexible Circuit Technology’, ‘Flexible Circuit Technology 2nd Edition’, ‘Flexible Circuit Handbook’, ‘Flip Chip Technologies’, ASM Electronic Materials Handbook’, ‘The Handbook of Tape Automated Bonding’, and ‘The Handbook of Electronic Packaging’. He also edited the book ‘In our Own Words – a people’s commentary on life in the former Soviet Union’, which he helped conceive and create during the time he spent in Russia in 1991-92.

Mr Fjelstad is a frequent international lecturer at industry workshops and seminars and serves on the board of editorial advisors for several industry journals including: Electronic Packaging & Production (US), Flexible Circuits Engineering (US) and Circuit World (UK). He is also past editorial director of Chip Scale Review (US), past section editor for Future Circuits International (UK), Component Section, and is author of the monthly column ‘Flexible Thinking’ published in Circuitree Magazine (US). Mr Fjelstad currently holds 33 US patents and more than 28 foreign patents. He has numerous other invention disclosures and a number of other patents currently pending issue. He is a member of the IPC, IMAPS, SMTA, IEEE, and the Future Society.

Dr Reza Ghaffarian has nearly 20 years of industrial and academic experience in mechanical, materials, and manufacturing process engineering. At the Jet Propulsion Laboratory (JPL), Quality Assurance Section, California Institute of Technology, he supports research and development activities in SMT, BGA, CSP and MEMS technologies for infusion into NASA’s missions. He has authored over 100 technical papers, guidelines on BGA and CSP, four book chapters, and numerous patentable innovations. He received his MS in 1979, Engineering degree in 1980, and PhD in engineering in 1982 from the University of California at Los Angeles (UCLA).

Young-Gon Kim is Director of Product Design at Tessera, Inc. As director, Dr Kim oversees all package design activities, including the following: TAB tape based conventional µBGA™ package design; two-metal based high I/O and high performance µBGA™ package design; high performance WAVE package design; FEM-based design optimisation for reliability enhancement; electrical parameter extraction; and electrical design optimisation for high frequency devices. He also serves on the Patent Committee and chairs the Patent Invention Committee.

Dr Kim received his PhD in mechanical engineering from the University of Texas at Austin. His area of research was microscopic and macroscopic understanding of solid state bonding for electronics packaging and was funded by the National Science Foundation and technically supported by 3M and MCC. Young-Gon Kim received his BS in mechanical engineering from Seoul National University in 1984.

Prior to joining Tessera in June 1998, Dr Kim led the Package R&D Group for LG Semicon (currently Hyundai Electronics). His primary research area was chip scale package (CSP) and solder joint reliability on board. His colleagues and he developed a lead frame based CSP–Bottom Leaded Plastic (BLP) package for DRAM packaging. This package became a JEDEC standard (JC11, MO-196). A standard pin-out for SDRAM was proposed at a JEDEC JC42 committee meeting. The BLP technology was licensed to multiple package assembly houses. Dr Kim served as session chairman for SEMI International conferences from 1996 to 1998, and he has been invited to deliver lectures and seminars for international conferences and universities. He has contributed more than 30 publications to refereed journals, conference proceedings, newspapers and technical magazines in the electronics packaging area.