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BALL GRID ARRAY & FINE PITCH PERIPHERAL INTERCONNECTIONS

A Handbook of Technology & Applications for Microelectronics/Electronics Manufacturing

by JENNIE S. HWANG

Pages--241+xii; Tables--68; Figures--186; Size--23 x 15 cm.
ISBN 0 901150 29 0

Code: EP28

Contents of this page:

Description
Some Worldwide Reviews
About the author
Table of Contents

Description

In response to the market demands of end-use products, the trends of IC technology continue to proceed towards increasing I/O counts and shrinking dimensions in the circuit lines of integrated circuits. To achieve the connection of high I/O counts to the outside circuitry, two primary IC packaging architectures are available: peripheral interconnections such as quad flat packs (QFPs) and array interconnections such as ball grid arrays (BGAs). Both BGAs and QFPs are expected to be prevalent IC packages today and in the future. The interconnecting solder material and manufacturing process required for these two types of package are most demanding. They are critically important to the overall performance and reliability of circuit assembly in the electronics industry.

This handbook, dedicated to the interconnection of both array and peripheral IC packages, covers all important aspects related to these packages and their interconnection to the motherboard. It includes material characteristics, assembly processes, package types, inspection/rework and commonly occurring defects and remedies on the production floor. The key factors related to the reliability of solder interconnections and common failure modes are discussed.

The book highlights the contrast and comparison between these two packages in technology and applications. The information is laid out in a concise fashion and provides readers with quick access to specific areas of interest. Readers will acquire an overall grasp of the subject as well as obtaining specific knowledge.

Some Worldwide Reviews

"The current interest in fine line assembly and the devices available for its implementation should alone make this book essential reading. That it is very readable and contains both theoretical and practical details with good diagrams, extensive references and a comprehensive bibliography should establish its position as a reference work for some considerable time to come."

Microelectronics International (UK)

About the author

Jennie S. Hwang received her PhD in materials science and metallurgical engineering from the Engineering School of Case Western Reserve University, an MS in liquid crystal organic chemistry from the Liquid Crystal Institute of Kent State University, and an MA in chemistry from Columbia University. She also has a bachelor’s degree in chemistry.

Her many years’ experience as a technology/business manager and researcher covering various industries has brought a breadth and depth of knowledge in materials and processes from both theoretical and practical aspects.

Dr Hwang has been a consultant to major OEM/SMT contract manufacturers and military contractors. She is an invited lecturer/speaker world wide and holds several US and overseas patents in the area of electronics solder technology. In addition to many papers, Dr. Hwang is the author of the book ‘Solder Paste in Electronics Packaging — Technology & Applications for Surface Mount, Hybrid Circuits and Component Manufacturing’, published by Van Nostrand Rheinhold, and a co-author of ‘Solder Joint Reliability’ (VNR), ‘Electronics Packaging and Interconnection Handbook’ (McGraw-Hill) and ‘Fine Pitch Technology Handbook’ (VNR).

Dr Hwang was elected to the International Materials Review Committee of the British Institute of Metals and American Society of Metals. She has served as a board director of the Surface Mount Technology Association and president of the association. Dr Hwang is on the advisory board to Surface Mount Technology Magazine and writes a monthly column for the magazine. She serves on the International Electrotechnical Commission (IEC) TC-91 Advisory Group working on surface mount standards and on the Government Relations’ Committee of IPC. She is an expert member of the American National Standards Institute.

Dr Hwang is a member of ISHM, American Ceramic Society, American Chemical Society, American Society of Metals, Surface Mount Technology Association, and Adhesion Society. She is at present the president/CEO of H-Technologies Group Inc., specialising in providing business and manufacturing solutions to the electronic/microelectronics interconnection industry. Prior to this appointment, she has held senior managerial and research positions with SCM Corporation, Martin Marietta Corporation and Sherwin-Williams Company and is the founder of IEM Corporation. She has recently been inducted as a Commodore by the Governor of the State of Ohio.

Table of Contents

Chapter 1

Introduction

1.1 General Background

1.2 Peripheral and Array Architecture

1.3 Merits and Limitations

1.3.1 Quad Flat Packs (QFPs)

1.3.2 Ball Grid Arrays (BGAs)

1.3.3 Cost Considerations

1.4 Utility of the Book

 

Chapter 2

Types of IC Packages

2.1 Array Packages

2.1.1 P-BGA

2.1.2 C-BGA

2.1.3 M-BGA

2.1.4 T-BGA

2.1.5 µ-BGA

2.2 Quad Flat Packs (QFPs)

2.3 PCMCIA

 

Chapter 3

Solder Material Characteristics

3.1 BGA Solder

3.2 Fine Pitch QFPs

3.3 Solder Intrinsic Physical Properties

3.3.1 Phase Transition Temperature

3.3.2 Electrical Conductivity

3.3.3 Thermal Conductivity

3.3.4 Coefficient of Thermal Expansion (CTE)

3.3.5 Surface Tension

3.4 Solder Intrinsic Metallurgical Properties

3.4.1 Plastic Deformation

3.4.2 Strain Hardening

3.4.3 Recovery

3.4.4 Recrystallisation

3.4.5 Solution Hardening

3.4.6 Precipitation Hardening and Softening

3.4.7 Superplasticity

3.5 Solder Intrinsic Mechanical Properties

3.5.1 Stress vs Strain Behaviour

3.5.2 Creep Resistance

3.5.3 Fatigue Resistance

Chapter 4

Assembly Process

4.1 Solder Deposition Techniques

4.2 Mass Printing Factors

4.3 Solder Paste Rheology

4.4 Stencil Selection

4.5 Printing Parameters

4.6 Mass Reflow Techniques

4.6.1 Soldering Principles

4.6.2 Reflow Temperature Profile

4.6.3 Measuring Temperature and Temperature Uniformity

4.7 Flux and Fluxing

4.7.1 Water-cleaning Flux Systems

4.7.2 No-clean Flux

4.7.3 Gas Phase Fluxing

4.7.4 Reduced Oxide Soldering Activation (ROSA)

4.7.5 Plasma Assisted Dry Soldering (PADS)

4.8 Solderability and Wettability

4.8.1 Wetting Principle

4.8.2 Solderability Factors

4.8.3 Solderability of Component Leads

4.8.4 Solderability of Palladium-coated Leads

4.8.5 Solderability Measurement

4.9 Aspects of BGAs

4.9.1 C-BGAs

4.9.2 P-BGAs and OMPACs

4.9.3 SLICCs

4.9.4 T-BGA

4.9.5 µ-BGA

4.9.6 Flip-on-flex

4.9.7 PCMCIA Card

4.10 Aspects of Fine Pitch QFPs

4.10.1 Solder Powder Selection

4.10.2 Stencil Thickness vs Stencil Aperture Dimensions

4.10.3 Stencil Aperture Design vs Land Pattern

4.10.4 Multiple Step Soldering

4.10.5 In-situ Chemical Reaction Precoating Methodology

4.11 Other Factors

Chapter 5

Common Issues and Concerns

5.1 Array Interconnections

5.1.1 Bridging

5.1.2 Open or Insufficient Solder

5.1.3 Poor Wetting

5.1.4 Solder Balls

5.1.5 Voids

5.1.6 Foreign Contamination

5.1.7 Package Cracks

5.1.8 Thermal Management

5.2 Fine Pitch Interconnections

5.2.1 Bridging

5.2.2 Open and Insufficient Solder Joints

5.2.3 Poor Wetting

5.2.4 Solder Balls

5.2.5 Voids

5.2.6 Foreign Contamination

5.2.7 Component Misalignment

5.2.8 Wicking

5.2.9 Tack Time vs Printability

 

Chapter 6

Inspection, Rework and Repair

6.1 General Perspective

6.2 Array Solder Interconnection Inspection

6.2.1 Examination of Solder Joints

6.2.2 Examination of Solder Paste Deposits prior to Reflow

6.2.3 Continual Improvement and Establishment of a Process System

6.3 Fine Pitch Solder Interconnection Inspection

6.3.1 Solder Joint Inspection

6.3.2 Component Placement Inspection

6.3.3 Solder Paste Deposition Inspection

6.3.4 Continuous Process Improvement

6.4 Rework and Repair

 

Chapter 7

Reliability of Solder Interconnections

7.1 Factors of Solder Joint Integrity

7.2 Basic Failure Processes

7.2.1 General Aspects of the Creep-fatigue Phenomenon

7.2.2 Rôle of Intermetallics

7.2.3 The Rôle of Gold

7.2.4 Microstructure vs Mechanical Properties

7.3 Common Solder Joint Failure Mode

7.3.1 Cracks Along or Near the Interface

7.3.2 Cracks Appearing in the Bulk of the Solder Joint

7.3.3 Cracks Initiated on the Free Surface

7.3.4 Other Solder Joint Failure Mode

7.3.5 Thermal Fatigue Failure Model vs Solder Joint Configuration

7.4 Array Solder Interconnection

7.4.1 Component

7.4.2 Board Material

7.4.3 Solder Composition

7.4.4 Configuration and Volume of Solder Joint

7.4.5 CTE match of Component, Board and Solder Material

7.4.6 Underfill Material

7.4.7 Manufacturing Process

7.5 Peripheral Solder Interconnections

7.5.1 Component

7.5.2 Solder Joint Volume and Configuration

7.5.3 Conformal Coating and Environment

7.6 PCMCIA Card Solder Interconnection

 

Chapter 8

Present and Future Perspectives

8.1 Industry Dynamics

8.2 Emerging or High Performance Electronics Packaging and Assembly Technologies

8.2.1 Flip Chip Technology

8.2.2 Tape Automated Bonding Technology

8.2.3 Chip-on-board Technologies

8.2.4 Multichip Modules

8.2.5 Hybrid of Array and Peripheral Architecture

8.3 Trends of Soldering and Solder Paste

8.3.1 Present and Future Perspectives

8.3.2 Environmentally Friendly Manufacture

8.4 Survey of PCB Assembly using SMT and Advanced Packages

8.5 Concluding Remarks

 

 

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 Page last revised 11.02.05

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