SURFACE MOUNT & MIXED TECHNOLOGY PCB DESIGN GUIDELINES

A Handbook for Professional Engineers

by David Boswell

Pages--89; Tables--30; Figures--101; Size--30 x 21 cm.
ISBN 1 872422 01 2

REFERENCE BOOKS

SECTION 1

Board Physical Structure

1.1 SM PCB Aspect Ratio and Thickness

1.2 PCB Base Material Option

1.3 Solder Resist Options

1.4 Mounting SM Assemblies into Equipment

1.5 Assessing Structural Integrity

1.6 Leadframe Assembly

SECTION 2

PCB Card Design for Mechanised Production

2.1 Fiducial Marks for Use on Automatic Pick & Place Machines

2.2 Planning for Step & Repeat

2.3 Specifying Location Holes in the Card

2.4 Scribing, Routing, Break-out and Cropping SM PCBs

2.5 Horizontal and Vertical Axis Constraints on Pick & Place Machines

2.6 Designing for Glue Placement and Glued Component Removal

2.7 Controlling Component Varieties and Values

2.8 Specifying SM PCBs. A Check List

SECTION 3

Soldering Processes and Sequences

3.1 General Guidance

3.2 Process Sequences, Mixed Technology (SM + TH) Single and Double-sided Assemblies

3.3 Process Sequences, Single and Double-sided Assemblies, SM Components Only

SECTION 4

SM PCB Layout Design Guidelines

4.1 General Points on Component Positioning

(i) Proximity to Edges of PCB

(ii) Proximity to Break-out Lugs

(iii) Component Pad and Track Proximity Guidelines

(iv) Layout for Wave Soldering

(v) Making Layouts Look Professional

(vi) Layout to Minimise Bow in Thin, Long, Narrow Boards

4.2 Individual Component Proximity Guidelines and Special Problems

(i) Resistors, Ceramic Chip Types

(ii) Capacitors, Ceramic Chip Types

(iii) Capacitors, Chip Electrolytic Types, e.g., Aluminium, Tantalum

(iv) MELF Passive Components

(v) Capacitors, Micropackaged SM Types — Electrolytic

(vi) Capacitors, Micropackaged SM Types — Wound or Stacked

(vii) MELF and Small Outline Diodes (SODs)

(viii) Small Outline Transistors (SOTs)

(ix) SO I/Cs (Small Outline) Plastic Packages with Gull Wing and J-leads

(x) PLCC (Plastic Leaded Chip Carrier) I/Cs with J-leads

(xi) Miniature PLCCs with Gull Wing Leads

(xii) Quadpack I/Cs (Plastic Quad Flatpacks) with Albatross Wing Leads

(i) Common Pads

(ii) Via Holes in Pads

(iii) Theft Pads for Wave Soldering

(iv) Thermal Capacity Balance to Avoid Chip ‘Tombstoning’

(v) Solder Theft Balance

SECTION 5

PCB Copper Track Width, Clearance and Termination Shapes

5.1 Track Widths and Gaps

5.2 Termination of Fine Tracks at Solder Pads

5.3 Pads for Leads not Used Electrically

5.4 Track Management, Fan-out and Proximity Guidelines

SECTION 6

Solder Resist Specification and Aperture Design

6.1 Selecting the Right Type of Solder Resist

(i) Soldering Process

(ii) Component Types and Spacing on the Board

(iii) Resist Thickness Requirements

(iv) PCB Material and Manufacturing Process

6.2 Resist Aperture Design

SECTION 7

Solder Paste Application

7.1 Methods of Depositing Solder Paste for Reflow

(i) Screen Printing

(ii) Dispensing

7.2 Design of Screen Apertures

(i) Controlling Printed Volume of Paste

(ii) Aperture Design for Selected Mask Materials

SECTION 8

Using Through-hole Components on Mixed Technology Boards

8.1 Layout Guidelines

8.2 Use of Plugs and Sockets

8.3 Design Constraints due to SM Processes

SECTION 9

Via Holes and Pads for Interlayer Connection (No Pins/Wires Through Holes)

9.1 Via Hole Sizes

9.2 General Guidance Points

9.3 Proximity Rules

9.4 Filled Vias

9.5 Unfilled Vias

9.6 Tented Vias

9.7 Buried Vias

9.8 Stacked Vias

9.9 Blind Vias

SECTION 10

Design for ‘In-circuit’ Electrical Testing

10.1 Pad Size and Location

10.2 Breakable Links and Shortable Pads

10.3 Single Versus Double-sided Test Hardware

10.4 Size/Cost Compromise

10.5 Fan-out from Termination Pads

10.6 Unused I/C Termination Pads

SECTION 11

Design for Visual Inspection

11.1 Inspection Methods and Equipment

11.2 Visual Inspection of Large Boards

11.3 Design Requirements

Design for Rework in Manufacture and Repair in the Field

12.1 Methods of Rework

12.2 Layout for Rework and Component Replacement

12.3 Repair in the Field

SECTION 13

Component Location ‘Ident’ and Board Marking

13.1 Specifying Idents on the Board

13.2 Specifying Board Numbering Method

SECTION 14

Some Thermal Considerations

14.1 Thermal Plot at CAD Stage

14.2 Locally Increasing Thermal Conductivity of PCBs

14.3 Thermal Breaks

SECTION 15

Leadframes

15.1 General

15.2 SIL (Single-in-line) Versions

15.3 DIL (Dual-in-line) Versions

SECTION 16

Surface Mount Assemblies for Low Temperature Applications

16.1 The Thermal Expansion Mismatch Problem

16.2 Methods of Reducing the Stress

16.3 Guidelines for Specific Component Types

SECTION 17

Some CAD Issues

17.1 General

17.2 Technical Inputs to the CAD System for SM Circuits

17.3 Technical Outputs from the CAD System for SM Circuits

17.4 Admin Inputs/Outputs from CAD for Planning and Costing Production

APPENDICES

Appendix A Component Area — Board Size Relationship

Appendix B Solder Pad Footprints for Passive SM Components

B1 Ceramic Chip Resistors

B2 Ceramic Chip Capacitors

B3 Aluminium Electrolytic Capacitors — Moulded Plastic Micropackages

B4 MELF Passive Components

B5 Tantalum Electrolytic Capacitors — Moulded Plastic Micropackages

B6 Wound/Stacked Foil Capacitors — Moulded Plastic Micropackages

B7 Leadframes

B8 Trimmer Resistors

Appendix C Solder Pad Footprints for SM Discrete Semiconductors

C1 MELF Diodes and Small Outline Diodes (SODs)

C2 SOT 223

C3 SOT 23

C4 SOT 143

C5 SOT 89

C6 SOT 192/82 and D-Pack

Appendix D Solder Pad Footprints for SM Semiconductor Integrated Circuits

D1 SO and VSO (Small Outline) JEDEC Plastic Packages with Gull Wing Leads

D2 SO (Small Outline) Japanese Plastic Packages with Gull Wing Leads

D3 SO (Small Outline) JEDEC Plastic Packages with J-leads

D4 PLCC (Plastic Leaded Chip Carrier) JEDEC Packages with J-leads

D5 Miniature PLCC Packages with Gull Wing Leads

D6 Quadpack Plastic Packages with Albatross Wing Leads

APPENDIX E Definitions and Abbreviations

APPENDIX F Bibliography